Regviz

NXP Semiconductors /LPC18xx /LCD /LPBASE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LPBASE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC18xx/LCD/LPBASE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED 0LCDLPBASE

Description

Lower Panel Frame Base Address register

Fields

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
LCDLPBASE

LCD lower panel base address. This is the start address of the lower panel frame data in memory and is doubleword aligned.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data